(1) Field of the Invention
The present invention relates to manufacturing of semiconductor devices in general, and in particular, to a silicide process for fabricating mixed mode, analog/digital (A/D) chips.
(2) Description of the Related Art
With the advent of ultra scale integration (ULSI), circuit features are continuing to shrink to 1/2 micrometer (um) or less. Consequently, the resistance and capacitance (RC) associated with interconnection paths in integrated circuits becoming more and more critical. This is particularly true with CMOS devices, in which the RC delay due to the interconnect paths can exceed the delays due to gate switching. As is well known, the higher the value of the interconnect RC constant, the more likely is the circuit operating speed to be limited by this delay. In other words, low resistivity interconnection paths are critical in order to fabricate dense, high performance devices.
There are several approaches to reduce the interconnect resistivity as explained in S. Wolf and R. N. Tauber, "Silicon Processing for the VLSI Era," vol. 2, Lattice Press, Sunset Beach, Calif., 1990, p. 384. One approach, for example, is to replace the commonly used interconnect material polysilicon with low resistance refractory metals. It will be known to workers in the field that polysilicon has replaced aluminum as an interconnect material because it can withstand high process temperatures, but it is a high resistance material. Refractory metals have adequately high melting temperatures, but their oxides are typically of poor quality. Thus, usually, a multilayer structure, called polycide, consisting of a low resistance refractory metal silicide on top of a doped polysilicon layer is formed for use as an interconnect. The refractory metal on the polysilicon is converted to a metal silicide by subjecting the multilayer structure to heat.
The silicide process, or silicidation, gains a special importance in integrated circuits containing both analog and digital circuits where interconnections are used between these two different types of circuits. For example, counterdiffusion of different types of dopants through poor and degraded silicide interconnects can be a problem. At the same time, ability to produce both types of circuit functions on the same chip can provide significant benefits. For example, CMOS (complimentary metal-oxide semiconductor), as is well known, can be used to minimize dc power dissipation and provide high-impedance FET (field effect transistor) inputs for certain functions while bipolar devices can provide high current gain capabilities. BiCMOS technology can take advantage of these special characteristics of both types of circuits, and permit the simultaneous fabrication of high-performance analog and digital functions on the same chip. It is also well known that high-performance capacitors play a significant role in BiCMOS chips, especially in the areas of A/D converters and switched-capacitor filters. (See S. Wolf and R. N. Tauber, "Silicon Processing for the VLSI Era," vol. 2, Lattice Press, Sunset Beach, Calif., 1990, p. 544).
A common type of capacitor typically formed within an analog integrated circuit is a dual layer polysilicon capacitor. Dual layer polysilicon capacitors are formed from two substantially planar conductive polysilicon electrodes separated by a dielectric layer. Dual layer polysilicon capacitors provide several advantages when used within chips having integrated analog and digital circuits. In addition, methods for forming dual layer polysilicon capacitors usually provide efficient manufacturing processes since the same one layer of the dual polysilicon capacitor can be used to form other polysilicon structures at other locations within the same integrated circuit. For example, it is common to form polysilicon or polycide gate electrodes within FET devices simultaneously with forming polysilicon or polycide contact within bipolar transistor electrodes on the same chip.
FIG. 1a shows the structure of a conventional dual layer polysilicon capacitor formed on semiconductor substrate (10). Active regions (20) and (20') in the substrate are defined by passive (isolation) regions (30) formed in and on the same substrate as shown in the same Figure. After the formation of the active and passive regions, a thin layer of oxide (40) is grown usually thermally followed by deposition of a first polysilicon layer (50) and then metal layer (60), though these layers are not shown in FIG. 1a. What are shown in the figure are columnar structures (1) and (2) that are formed from these layers respectively, by using the well-known techniques of masking and etching; namely, metal cap (61) over an FET polysilicon gate (51) separated from active region by gate oxide (40), and similarly, metal cap (61') over a first polysilicon electrode of a dual layer polysilicon capacitor residing over isolation region (30) where thermal oxide is also a part. Metal caps (61) and (61'), are next subjected to heating to react with silicon in polysilicon portions (51) and (51') to form silicide with polysilicon, or polycide. The metal is usually selected from a refractory group consisting of tungsten, titanium, tantalum, molybdenum, and platinum and can either be deposited as a pure metal on a silicon bearing surface, or co-evaporated with silicon. Silicides have the characteristics of low electrical resistivity, ease of formation, smooth surface features and good corrosion resistance (See S. Wolf and R. N. Tauber, "Silicon Processing for the VLSI Era," vol. 1, Lattice Press, Sunset Beach, Calif., 1990, p. 386). Following the silicide formation, active regions are implanted with impurities to form the source/drain regions (20) and (20') shown in FIG. 1a.
Thus, at the same time that an FET (1) polycide gate (1) is formed, the first polysilicon electrode of a dual layer polysilicon capacitor (2) is also formed. Subsequently, formed upon the patterned metal silicide layer (61') is a patterned insulator layer (70), and formed upon the patterned insulator layer (70) is a patterned second polysilicon layer (80). The patterned second polysilicon layer (80) forms the second polysilicon electrode of the dual layer polysilicon structure of FIG. 1a. Further processing then takes place to complete the circuit, by continuing with steps well known in the art, that is, by forming interconnects (90) and (90') to source/drain regions (20), (20'), respectively, (93) to polycide gate (51) and (61), and (95) to the second polysilicon electrode (80) of the dual layer capacitor as shown in FIG. 1a.
It will be known to those skilled in the art that the properties of the patterned insulator layer (70)--also known as inter-poly oxide (TPO)--as well as its thickness, play a significant role in determining the storage capacity of capacitors, in general. Thus, IPO (70) is usually very thin and is formed of a dielectric material selected from a group consisting of silicon oxide, silicon nitride, and silicon oxynitride. IPO is sometimes characterized as a high temperature oxide (HTO) and is deposited by chemical vapor deposition and later densified at even higher temperatures.
Conventional capacitor structures such as shown in FIG. 1a and some associated problems are discussed by Chang, et al in U.S. Pat. No. 5,631,188. Chang essentially follows the same process steps of fabricating a polysilicon capacitor which are shown diagrammatically in FIG. 1b. Namely, in step (110), a substrate with active and passive regions is provided. Gate oxide is next thermally grown, followed by the blanket deposition of a first polysilicon layer and a refractory metal (step (150)). The blanket layers are then patterned and etched (step (151)) to form simultaneously FET gate (1) and the first electrode of the dual layer capacitor (2) shown in FIG. 1a. Refractory metal residing over gate (51) and first polysilicon electrode (51') is next silicidated by subjecting it to heat. Using the silicidated areas as a mask, source/drain regions are formed through implantation of impurities. In step (170), a thin layer of IPO is deposited followed by the depositing of the second polysilicon layer in step (180). Further processing takes place in steps (175) and (190) to complete the circuit, where ILD is deposited and interconnections are made to the source/drain regions, to the gate and to the dual layer capacitor.
Chang in U.S. Pat. No. 5,631,188 cites the problem of delamination between the patterned silicide cap (61') and the patterned first polysilicon layer (51') of prior art, and teaches a method of forming the silicide independent of the polysilicon layer so as to prevent the delamination. He also proposes a method of forming a low voltage coefficient capacitor within an integrated circuit. (It is generally known that voltage coefficients of less than 50 ppm/V are desirable). Lavene, on the other hand, teaches a method for making metallized capacitor having increased dielectric breakdown voltage in U.S. Pat. No. 5,641,111. Hashizume, et al, propose in U.S. Pat. No. 5,604,145, a method to improve capacitances of capacitors in a DRAM. Tang, et al., in U.S. Pat. No. 5,010,032 address the problem of counterdiffusion of dopants, that is, impurities, through connections between p+ and n+ polysilicon levels in a mixed mode CMOS device which includes metal suicides and nitride interconnects, especially in the ULSI technology where the interconnect lengths are very short and still shrinking, thus bringing the differently doped areas ever closer together.
A problem that is not addressed in prior art concerns the degradation of the silicide metal at the time of interpoly (IPO) deposition (step (170)) after the silicidation step (160). It is found in the present line of manufacturing that the degraded silicide metal can contribute to higher resistivity of the polysilicon electrodes, high voltage coefficient and space-charge capacitance of the dual layer capacitor, as well as to the counterdiffusion of dopants between mixed, that is, analog/digital devices. It is disclosed in the embodiments of this invention that these problems can be alleviated.